The present invention relates to an electrically erasable and programmable read-only memory (EEPROM), and more particularly to a program (write) optimizing circuit and method for EEPROM.
A recent EEPROM consists of as a memory cell a floating gate field effect transistor doubly deposited gates, of which one is a control gate for receiving an external voltage, and the other is a floating gate formed with insulation between the control gate and the channel region, so that a high voltage of a given level may be applied to a selected word line of the memory cell so as to make the floating gate into an enhancement type for erasing, while to make the transistor of the memory cell into a depletion type for program.
Generally, the program is performed in pages in order to reduce the write time. The page is referred to as all the memory cells connected to a word line that are in a row. Hence, if a word line is selected by a row decoder, a high voltage of a given level is applied to the drains of the memory cells whose control gates are connected to the selected row, so that a program is made.
However, in an EEPROM employing a NAND type memory cell array in which a plurality of memory cells constitute the unit of a memory string through a common string select transistor and ground select transistor, the channels of the memory cells are connected in series between the string select transistor and ground select transistor, so that when the word line selected for programming a memory cell of the memory string is grounded and a high voltage is applied to the bit line, the memory cells connected to the word lines not selected must be prevented from being undesirably programmed by the high voltage. Hence, there has been disclosed a method for applying a voltage of a given level to the word lines and bit lines of the memory cell not selected in order to prevent the undesired program.
Most recently, there has been disclosed an article entitled as "A 5V-Only One-transistor 256K EEPROM with Page-Mode Erase" written by Takeshi Nakayama, et al. in Pages 911-915, IEEE Journal of Solid--State Circuits, August 1989. The circuit and the operation timing diagram thereof concerning program and anti-program disclosed in the article are depicted in FIGS. 1 and 2.
Referring to FIG. 1, a pump circuit 20 for programming and a pump circuit 30 for anti-programming are connected to each bit line BL of EEPROM memory cell 50. A discharge transistor 25, whose gate is connected to a control signal BLR, makes the bit line be connected to a ground voltage terminal while erasing. The program pump circuit 20 is a charge pump comprising two NMOS transistors 24, 26 and a capacitor 27. The pumping clock .phi. applied to the capacitor 27 is delivered or blocked to the program pump circuit 20 through an NMOS transistor 22. The gate of the gating NMOS transistor 22 is connected to the output of a latch circuit 60. The latch circuit 60 stores the data received before programming of the memory cell, thus applying or blocking a high program voltage VBPP to the corresponding bit line according to the state of the data.
Namely, since the output of the latch circuit 60 is connected to the gate of the gating NMOS transistor 22, if the stored data is "0", the pumping clock .phi. is not applied to the program pump circuit 20 for the bit line voltage not to be raised, while if the data is "1", the pumping clock .phi. is applied to the capacitor 27 for the bit line to receive a program voltage of high level VBPP. The data is transmitted to the latch circuit 60 through a transfer transistor 23 with the channel connected between the bit line and the input (or output) of the latch circuit and with the gate connected to a data transfer signal PLW.
On the other hand, the gate of a voltage transfer transistor 21 whose channel is connected between the bit line and anti-program voltage VBPI is connected to a program signal PGM and the anti-program pump circuit 30. The anti-program pump circuit 30 is a charge pump comprising two NMOS transistors 31 32 and a capacitor 33 as similarly as the program pump circuit 20, and produces the anti-program voltage VBPI on one third level of the voltage (about 15 V) used for practical programming when the program pump circuit 20 does not provide the program voltage VBPP to the corresponding bit line according to the data of the latch circuit 60 being "0". Namely, the anti-program pump circuit 30 is to prevent programming to the bit lines of the memory cell not selected.
Here, the program pump circuit 20, anti-program pump circuit 30, latch circuit 60, gating transistor 22, voltage transfer transistor 21, transfer transistor 23 and discharge transistor 25 are the circuit elements connected to a single bit line, which are provided for each bit line of a memory array with a plurality of bit lines.
In addition, a word line pump circuit 40 is connected between the word line WL of the memory cell 10 and a row decoder 50 for providing an erasing voltage (about 15 V) of high level to the word line selected while erasing. The word line pump circuit 40 is a kind of charge pump comprising two NMOS transistors 41, 42 and a capacitor 43, and generates the word line voltage VWPP about 15 V to the word line selected by the row decoder 50 while erasing, and generates the word line voltage VWPP on two thirds level of 15 V if the word line is not selected.
Between the common source line 11 of the memory cell 10 and the ground voltage terminal is connected a ground connecting transistor 12 to ground the source of the memory cell when erasing and programming. The control signal CLE applied to the gate of the ground connecting transistor 12 is also applied to the latch circuit 60, and becomes high to only enable the latch circuit 60 during the data being transmitted, erased and programmed, but data being read, makes the common source line of the memory cell be connected to the ground voltage terminal through the ground connecting transistor 12. A column select transistor 14 serves to connect the bit line to an input/output data line 15 by a Y gating signal 13 appeared from the column decoder.
Hereinafter will be described the erasing and programming functions of the structure of FIG. 1 with reference to the timing diagram of FIG. 2.
Referring to FIG. 2, if the control signal (a) to control the latch circuit 60 and the ground connecting transistor 12 becomes "high" state, data transfer signal (b) becomes "high" state for a short time, at this time, a data given from the data input/output line 15 is stored in the latch circuit 60. Then, during the erasing time (TER), the control signal (c) applied to the gate of the discharge transistor 25 maintains "high" state, making the bit line into the ground level, and the word line pump circuit 40 pumps the word line voltage (e) about 15 V as the pumping voltage VPP to the word line selected in order to erase the data of the selected memory cell.
Thereafter, if the internal timer steps into the programming time TPG, the program signal (d) is enabled as "high" state. At this time, if the information stored in the latch circuit 60 is "1" state, the program pump circuit 20 of FIG. 1 works to raise the program voltage (f) to the pumping voltage VPP, which is applied to the corresponding bit line so as to store the data "1" in the selected memory cell. Conversely, if the data stored in the latch circuit 60 is "0" state, the gating transistor 22 is turned off, so that the program pump circuit 20 cannot perform the pumping function. Instead, the program signal (d) of "high" state causes the anti-program pump circuit 30 to pump the anti-program voltage (g) of one third of the VPP level to the bit line. On the other hand, the word line selected by the row decoder 50 becomes the ground level, while to the word line not selected is applied the word line voltage (e) of two thirds of the VPP level. Reading of the cell erased or programmed is made possible by detecting the current flowing through the memory cell when the source voltage 5 V is applied to the word line, a voltage of about 2 V is applied to the bit line and the source is grounded.
Although the above conventional circuit works to maintain a suitable program state, each bit line of the memory array should include a program pump circuit 20, anti-program pump circuit 30 and latch circuit 60 as shown in FIG. 1, so that the area of the memory chip is considerably increased so as to impede high integration of the memory, and there are caused the problems in connection with the yield rate and production cost.